As memory densities of semiconductor memory continue to increase, maintaining or decreasing memory access times and power consumption may be more challenging with conventional memory array architecture. Some physical dimensions of the memory circuitry may increase while other dimensions may be reduced in increasing memory density, in many instances resulting in challenges to fabrication and operation of the memory. For example, various signal lines, such as input/output lines, and control signal lines of a memory may need to extend over greater physical distances (e.g., longer signal lines) while having other physical dimensions reduced (e.g., width, spacing, pitch, etc.). The resulting signal lines have increased capacitance and are more difficult to drive to desired voltage levels. That is, it may require more time to drive the signal lines to the desired voltage levels.
Additional circuits or circuits having greater drivability have been included in memories to address increased signal line resistance and capacitance. However, including the additional circuits and circuits with increased drive require greater physical space on the memory, and may result in increased power consumption. Given that low power consumption, compactness, and relatively fast access times are desirable for current and future memories, conventional approaches to addressing shortcomings of known memory array architectures may be unacceptable.